/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/** *****************************************************************************************************
 *  \file     device.h                                                                        *
 *  \brief    This file contains the device information                                       *
 *                                                                                                      *
 * <table>                                                                                              *
 * <tr><th>Date           <th>Version                                                                   *
 * <tr><td>2023/09/09     <td>1.0.0                                                                     *
 * </table>                                                                                             *
 *******************************************************************************************************/

#ifndef E3_DEVICE_H
#define E3_DEVICE_H

#include "regs_base.h"

#define CPU_INDEX_0             0U
#define CPU_INDEX_1             1U
#define CPU_INDEX_2             2U
#define CPU_INDEX_3             3U
#if !defined(E3650_BOOTLOADER)
#define CPU_MAX_CORE_NUMBER     4U
#else /* #if !defined(E3650_BOOTLOADER) */
#define CPU_INDEX_SE            4U
#define CPU_INDEX_LP            5U
#define CPU_MAX_CORE_NUMBER     6U
#endif /* #if !defined(E3650_BOOTLOADER) */

#if defined(CPU_cortex_r5)
#ifndef CACHE_SIZE
#define CACHE_SIZE              32U
#endif
#ifndef CACHE_LINE
#define CACHE_LINE              32U
#endif
#elif defined(CPU_cortex_r52)
#ifndef CACHE_SIZE
#define CACHE_SIZE              64U
#endif
#ifndef CACHE_LINE
#define CACHE_LINE              64U
#endif
#endif /* #if defined() */

/* R52 core0  */
#define CORE0_TCMA_BASE    (0x11000000UL)
#define CORE0_TCMA_SIZE    (0x8000UL)

#define CORE0_TCMB_BASE    (0x11100000UL)
#define CORE0_TCMB_SIZE    (0x8000UL)

#define CORE0_TCMC_BASE    (0x11200000UL)
#define CORE0_TCMC_SIZE    (0x10000UL)

/* R52 core1  */
#define CORE1_TCMA_BASE    (0x11400000UL)
#define CORE1_TCMA_SIZE    (0x8000UL)

#define CORE1_TCMB_BASE    (0x11500000UL)
#define CORE1_TCMB_SIZE    (0x8000UL)

#define CORE1_TCMC_BASE    (0x11600000UL)
#define CORE1_TCMC_SIZE    (0x10000UL)

/* R52 core2  */
#define CORE2_TCMA_BASE    (0x11800000UL)
#define CORE2_TCMA_SIZE    (0x8000UL)

#define CORE2_TCMB_BASE    (0x11900000UL)
#define CORE2_TCMB_SIZE    (0x8000UL)

#define CORE2_TCMC_BASE    (0x11a00000UL)
#define CORE2_TCMC_SIZE    (0x10000UL)

/* R52 core3  */
#define CORE3_TCMA_BASE    (0x11c00000UL)
#define CORE3_TCMA_SIZE    (0x8000UL)

#define CORE3_TCMB_BASE    (0x11d00000UL)
#define CORE3_TCMB_SIZE    (0x8000UL)

#define CORE3_TCMC_BASE    (0x11e00000UL)
#define CORE3_TCMC_SIZE    (0x10000UL)

#define VERSION_REG_ADDR   (APB_EFUSEC_BASE+0x1018UL)
#define V_MAJOR_MASK       (0x00f00000U)
#define V_MAJOR_POS        (20U)
#define V_MINOR_MASK       (0x000f0000U)
#define V_MINOR_POS        (16U)
#define GET_MINOR_V(v)     ((uint8)(((v) & V_MINOR_MASK) >> V_MINOR_POS))
#define GET_MAJOR_V(v)     ((uint8)(((v) & V_MAJOR_MASK) >> V_MAJOR_POS))

#endif
